1. Field of the Invention
Generally, the present disclosure relates to the formation of microstructures, such as advanced integrated circuits, and, more particularly, to the formation of conductive structures, such as copper-based metallization layers, and techniques to reduce electromigration during operation.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these inter-connect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area, as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, a plurality of stacked “wiring” layers, also referred to as metallization layers, is usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the inter-connect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like. The reduced cross-sectional area of the interconnect structures, possibly in combination with an increase of the static power consumption of extremely scaled transistor elements, may result in considerable current densities in the metal lines, which may even increase with every new device generation.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Operating the interconnect structures at elevated current densities, however, may entail a plurality of problems related to stress-induced line degradation, which may finally lead to a premature failure of the integrated circuit. One prominent phenomenon in this respect is the current-induced mass transport in metal lines and vias, also referred to as “electromigration.” Electromigration is caused by momentum transfer of electrons to the ion cores, resulting in a net momentum in the direction of electron flow. In particular at high current densities, a significant collective motion or directed diffusion of atoms may occur in the interconnect metal, wherein the presence of respective diffusion paths may have a substantial influence on the displaced amount of mass resulting from the momentum transfer. Thus, electromigration may lead to the formation of voids within and hillocks next to the metal interconnect, thereby resulting in reduced performance and reliability or complete failure of the device. For instance, aluminum lines embedded into silicon dioxide and/or silicon nitride are frequently used as metal for metallization layers, wherein, as explained above, advanced integrated circuits having critical dimensions of 0.1 μm or less, may require significantly reduced cross-sectional areas of the metal lines and, thus, increased current densities, which may render aluminum less attractive for the formation of metallization layers.
Consequently, aluminum is being replaced by copper and copper alloys, a material with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine and the like, into the copper. Furthermore, the conductive barrier layers may also provide highly stable interfaces with the copper, thereby reducing the probability for significant material transport at the interface, which is typically a critical region in view of increased diffusion paths. Currently, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, in addition to the fact that copper may not be efficiently patterned by anisotropic dry etch processes, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less, in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability. In particular, it is important to identify, monitor and reduce degradation and failure mechanisms in interconnect structures for various configurations to maintain device reliability for every new device generation or technology node.
Accordingly, a great deal of effort has been made in investigating the degradation of copper interconnects, especially in combination with low-k dielectric materials having a relative permittivity of 3.1 or even less, in order to find new materials and process strategies for forming copper-based lines and vias with a low overall permittivity. Although the exact mechanism of electromigration in copper lines is still not quite fully understood, it turns out that voids positioned in and on sidewalls and especially at interfaces to neighboring materials may have a significant impact on the finally achieved performance and reliability of the interconnects.
One failure mechanism, which is believed to significantly contribute to a premature device failure, is the electromigration-induced material transport, particularly along an interface formed between the copper and a dielectric cap layer, which may be provided after filling in the copper material in the trenches and via openings, the sidewalls of which are coated by the conductive barrier materials. In addition to maintaining copper integrity, the dielectric cap layer may usually act as an etch stop layer during the formation of the via openings in the interlayer dielectric. Frequently used materials are, for example, silicon nitride and silicon carbon nitride, which exhibit a moderately high etch selectivity to typically employed interlayer dielectrics, such as a plurality of low-k dielectric materials, and also suppress the diffusion of copper onto the interlayer dielectric. Recent research results seem to indicate, however, that the interface formed between the copper and dielectric cap layer is a major diffusion path for material transport during operation of the metal interconnect.
Consequently, a plurality of alternatives have been developed in an attempt to enhance the interface characteristics between the copper and the cap layer having the capability of reliably confining the copper and maintaining its integrity. For example, it has been proposed to selectively provide conductive materials on top of the copper-containing region, which may exhibit superior electromigration performance while not unduly reducing the overall resistance of the corresponding metal line. For instance, a compound of cobalt/tungsten/phosphorous (CoWP) has proven to be a promising candidate for conductive cap layers, which may significantly reduce electromigration effects within a corresponding metal line.
Although the compound of cobalt/tungsten/phosphorous provides superior electro-migration performance and may be efficiently implemented into the overall process flow for manufacturing complex metallization systems, since this compound may be readily deposited on the basis of selective electrochemical deposition recipes, it turns out, however, that severe defects may be observed during the patterning of vias connecting to metal regions having formed thereon the cobalt/tungsten/phosphorous cap layer, as will be described in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 at an advanced manufacturing stage, i.e., during a manufacturing sequence for forming a metallization system. The semiconductor device 100 comprises a substrate 101, which may include circuit elements (not shown) according to the specific circuit configuration of the device 100. The semiconductor device 100 may further comprise a first metallization level 110 and a second metallization level 120. As previously explained, the metallization layer 110 may comprise a dielectric material 111, for instance in the form a low-k dielectric material, in which is formed a metal line 112 comprised of copper, in combination with a barrier layer 112A, for instance in the form of tantalum nitrite, tantalum and the like. Moreover, a top surface 112S of the metal region 112 has formed thereon a conductive cap layer 113 comprised of the ternary alloy cobalt/tungsten/phosphorous (CoWP). Furthermore, a dielectric etch stop layer 114, for instance in the form of silicon dioxide, silicon carbide, nitrogen-containing silicon carbide and the like, is formed above the dielectric material 111 and partially above the metal line 112 in contact with the conductive cap layer 113. The further metallization layer 120 comprises, in the manufacturing stage shown, a dielectric material 121 of any appropriate composition, in which is formed a via opening 121A, wherein the dielectric material 121 may represent a lower portion of a dielectric layer stack for the layer 120, if a single damascene strategy is considered, or a trench (not shown) may be formed in the upper portion of the dielectric layer 121.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of well-established process techniques, including the formation of circuit elements (not shown) followed by the fabrication of an appropriate contact structure above which a plurality of metallization layers, such as the layers 110, 120 may be formed. For this purpose, the dielectric material 111 may be deposited, for instance, by chemical vapor deposition (CVD) and the like, followed by a patterning sequence for forming an appropriate trench in the layer 110, possibly in combination with respective via openings (not shown), depending on the overall process strategy. A respective etch process for forming a via opening will be discussed with reference to the via opening 121A. Next, the barrier layer 112A may be formed and subsequently the copper material may be filled in, for instance, by electroplating, which may possibly require the deposition of an appropriate seed layer. Thereafter, any excess material of the copper and the barrier layer 112A may be removed, for instance by electrochemical etch techniques, chemical mechanical polishing (CMP) and the like. Subsequently, the exposed surface 112S may be “passiviated” by depositing the conductive cap layer 113, thereby also providing the desired strong interface at the surface 112S in view of superior electromigration performance, as previously discussed. The deposition of the CoWP alloy may be accomplished by electroless plating, during which the exposed surface 112S may act as a catalyst material for initiating the electrochemical reaction when exposed to an appropriate electrolyte solution. Thus, a self-aligned deposition mechanism may be obtained, since the deposition is substantially restricted to the exposed copper surface 112S. After depositing a desired thickness, for instance approximately 10-50 nm, the dielectric etch stop layer 114 may be deposited, for instance, by CVD, followed by the deposition of the dielectric material 121. Next, a complex patterning sequence may be performed, which finally results in the via opening 121A so as to extend down to and into the dielectric etch stop layer 114, which may finally be opened on the basis of well-established etch recipes.
As is well known, during complex plasma-assisted etch processes, a plurality of etch byproducts may be generated, at least some of which may also deposit on exposed surface areas and which may have to be removed prior to a subsequent deposition of a material, such as a conductive barrier material within the opening 121A. Consequently, respective wet chemical etch recipes 115 may be applied, such as diluted hydrofluoric acid, ammonia peroxide mixtures and the like, which have proven to be efficient recipes for conditioning exposed surface portions prior to the further processing of the device 100. Consequently, during the process 115, an exposed portion of the conductive cap layer 113 may come into contact with wet chemical etchant, which, however, may result in undue material removal, thereby substantially completely removing the exposed portion of the cap layer 113 and also creating a significant under-etched area adjacent to the via opening 121A.
FIG. 1b schematically illustrates the semiconductor device 100 after the wet chemical cleaning process 115. As illustrated, a significant under-etching 113A may occur, thereby producing respective voids in the layer stack of the metallization system 120, which may thus result in process non-uniformity during the further processing, thereby also degrading overall performance of the via after filling the same with a barrier material and copper. Consequently, significant efforts have been made to substantially avoid the creation of the under-etched areas 113A, for instance, by finding wet chemical etch chemistries for efficiently cleaning the structure after a plasma-assisted etch process, substantially without attacking the cobalt/tungsten/phosphorous alloy. However, respective wet chemical etch chemistries may suffer from reduced efficiency. In other approaches, a further deposition process for forming the CoWP alloy in the under-etched areas 113A may be used, thereby significantly contributing to the overall cycle time due to a further wet chemical deposition step.
The present disclosure is directed to various methods and techniques that may avoid, or at least reduce, the effects of one or more of the problems identified above.